Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One prior art non-volatile memory cell 10 is shown in FIG. 1. The split gate SuperFlash (SF) memory cell 10 comprises a semiconductor substrate 1 of a first conductivity type, such as P type. The substrate 1 has a surface on which there is formed a first region 2 (also known as the source line SL) of a second conductivity type, such as N type. A second region 3 (also known as the drain line) also of a second conductivity type, such as N type, is formed on the surface of the substrate 1. Between the first region 2 and the second region 3 is a channel region 4. A bit line (BL) 9 is connected to the second region 3. A word line (WL) 8 (also referred to as the select gate) is positioned above a first portion of the channel region 4 and is insulated therefrom. The word line 8 has little or no overlap with the second region 3. A floating gate (FG) 5 is over another portion of the channel region 4. The floating gate 5 is insulated therefrom, and is adjacent to the word line 8. The floating gate 5 is also adjacent to the first region 2. A coupling gate (CG) 7 (also known as control gate) is over the floating gate 5 and is insulated therefrom. An erase gate (EG) 6 is over the first region 2 and is adjacent to the floating gate 5 and the coupling gate 7 and is insulated therefrom. The erase gate 6 is also insulated from the first region 2.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate EG 6 with other terminals equal to zero volt. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state. Another embodiment for erase is by a applying a positive voltage Vegp on the erase gate EG 6, a negative voltage Vcgn on the coupling gate CG 7, and others terminal equal to zero volts. The negative voltage Vcgn couples negatively the floating gate FG 5, hence less positive voltage Vcgp is required for erasing. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition (cell state ‘1’). Alternately the wordline WL 8 (Vwle) and the source line SL 2 (Vsle) can be negative to further reduce the positive voltage on the erase gate FG 5 needed for erase. The magnitude of negative voltage Vwle and Vsle in this case is small enough not to forward the p/n junction. The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate CG 7, a high voltage on the source line SL 2, a medium voltage on the erase gate EG 6, and a programming current on the bit line BL 9. A portion of electrons flowing across the gap between the word line WL 8 and the floating gate FG 5 acquire enough energy to inject into the floating gate FG 5 causing the floating gate FG 5 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as ‘0’ state.
The cell 10 can be inhibited in programming (if, for instance, another cell in its row is to be programmed but cell 10 is to not be programmed) by applying an inhibit voltage on the bit line BL 9. A split gate flash memory operation and various circuitry are described in U.S. Pat. No. 7,990,773, “Sub Volt Flash Memory System,” by Hieu Van Tran, et al, and U.S. Pat. No. 8,072,815, “Array of Non-Volatile Memory Cells Including Embedded Local and Global Reference Cells and Systems,” by Hieu Van Tran, et al, which are incorporated herein by reference.
FIG. 2 depicts a typical prior art architecture for a two-dimensional prior art flash memory system. Die 12 comprises: memory array 15 and memory array 20 for storing data, the memory array optionally utilizing memory cell 10 as in FIG. 1; pad 35 and pad 80 for enabling electrical communication between the other components of die 12 and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip or macro interface pins (not shown) for interconnecting to other macros on a SOC (system on chip); high voltage circuit 75 used to provide positive and negative voltage supplies for the system; control logic 70 for providing various control functions, such as redundancy and built-in self-testing; analog circuit 65; sensing circuits 60 and 61 used to read data from memory array 15 and memory array 20, respectively; row decoder circuit 45 and row decoder circuit 46 used to access the row in memory array 15 and memory array 20, respectively, to be read from or written to; column decoder 55 and column decoder 56 used to access the column in memory array 15 and memory array 20, respectively, to be read from or written to; charge pump circuit 50 and charge pump circuit 51, used to provide increased voltages for program and erase operations for memory array 15 and memory array 20, respectively; high voltage driver circuit 30 shared by memory array 15 and memory array 20 for read and write (erase/program) operations; high voltage driver circuit 25 used by memory array 15 during read and write operations and high voltage driver circuit 26 used by memory array 20 during read and write (erase/program) operations; and bitline inhibit voltage circuit 40 and bitline inhibit voltage circuit 41 used to un-select bitlines that are not intended to be programmed during a write operation for memory array 15 and memory array 20, respectively. These functional blocks are understood by those of ordinary skill in the art, and the block layout shown in FIG. 2 is known in the prior art.
With reference to FIG. 3, a prior art embedded flash memory system 100 is depicted. Embedded flash memory system 100 comprises power management unit 101, microcontroller unit core 102, peripherals 103 (USBx, SPI,I2C,UART,ADC,DAC,PWM,MC,HMI), SRAM 104, embedded flash device 105, and power supply bus 106. Embedded flash device 105 optionally can follow the design of FIGS. 1 and 2, described above. Power management unit 101 generates a plurality of voltages that are provided on power supply bus 106. Three examples of voltages provided on power supply bus 106 are VDD, VDDCORE, and VDDFLASH. VDD commonly is relatively high, such as 2.5 V, VDDCore is relatively low, such as 1.2 V, and VDDFLASH is also relatively high, such as 2.5 V, and in some cases is equal to VDDCORE. VDDCORE often is used to power the control logic of embedded flash memory system 100. VDD often is used to power all other functions.
With reference to FIG. 4, a typical power sequence operation is depicted for prior art embedded flash memory system 100. During a power-up sequence, at time TU0, the voltage for Voltage 401 begins to ramp up. At time TU1, the voltage for Voltage 402 begins to ramp up At time TU2, the voltage for Voltage 401 begins to plateau. At time TU3, the voltage for Voltage 402 begins to plateau. Here, Voltage 401 can be VDD, and Voltage 402 can be VDDFLASH.
During a power-down sequence, at time TD0, the voltage for Voltage 402 begins to ramp down. At time TD1, the voltage for Voltage 401 begins to ramp down. At time TD2, the voltage for Voltage 402 reaches 0 V. At time TD3, the voltage for Voltage 401 reaches 0 V.
The prior art power sequencing of FIG. 4 can be problematic. Specifically, in the period between time TU0 and TU1, Voltage 401 may reach a sufficient operating level while Voltage 402 is not at a sufficient operating level. Similarly, in the period between time TU1 and TU2, Voltage 401 may be at a sufficient operating level while Voltage 402 is not yet at a sufficient operating level. In the time period between time TD0 and TD1, Voltage 401 will still be at a sufficient operating level, but Voltage 402 may fall below a sufficient operating level. Between time TD1 and TD2, Voltage 402 will be below a sufficient operating level for at least part of that period while Voltage 401 will still be above a sufficient operating level. Between time TD2 and TD3, Voltage 402 will be below a sufficient operating level, and Voltage 401 may still be at a sufficient operating level for at least part of the period. These inconsistencies of state for Voltage 401 and Voltage 402 can cause problems in the operation of prior art embedded flash memory system 100. For example, logic circuits may not be able to operate before other circuits (such as a charge pump) are ready to operate.